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HT9032C/HT9032D
Calling Line Identification Receiver
Features
* Operating voltage: 3.5V~5.5V * Bell 202 FSK and V.23 demodulation * Ring detection input and output * Carrier detection output * Power down mode * High input sensitivity * HT9032C: 16-pin DIP/SOP package
HT9032D: 8-pin DIP/SOP package
Applications
* Feature phones * Caller ID adjunct boxes * Fax and answering machines * Computer telephony interface products * ADSI products
General Description
The HT9032 calling line identification receiver is a low power CMOS integrated circuit designed for receiving physical layer signals transmitted according to Bellcore TR-NWT-000030 and ITU-T V.23 specifications. The primary application of this device is for products used to receive and display the calling number, or message waiting indicator sent to subscribers from the central office facilities. The device also provides a carrier detection circuit and a ring detection circuit for easier system applications.
Block Diagram
T IP R IN G B and P ass . ilte r
D e m o d u la to r
PDW N PowerUp L o g ic
V a lid D a ta D e te c tio n
DOUTC DOUT CDET
R T IM E
In te rn a l PowerUp L o g ic RDET1 RDET2 R in g A n a ly s is C ir c u it RDET
VDD VSS
R e fe re n c e V o lta g e
C lo c k G e n e ra to r
X1 X2
Rev. 1.40
1
September 30, 2002
HT9032C/HT9032D
Pin Assignment
T IP R IN G 2 3 4 5 6 7 8 RDET1 RDET2 TEST R T IM E PDW N VSS 1 16 15 14 13 12 11 10 9 VDD DOUTC DOUT CDET RDET NC X1 X2 DOUT VDD T IP 3 6 4 5 R IN G 2 7 1 8 X1 X2 VSS PDW N
H T9032C 1 6 D IP -A /S O P -A
H T9032D 8 D IP -A /S O P -A
Pin Description
Pin Name Power Inputs VDD VSS PDWN Clock X1 X2 I O A crystal or ceramic resonator should be connected to this pin and X2. This pin may be driven from an external clock source. A crystal or ceramic resonator should be connected to this pin and X1. It detects ring energy on the line through an attenuating network and enables the oscillator and ring detection. This is a Schmitt trigger input. It couples the ring signal to the precision ring detector through an attenuating network. RDET=0 if a valid ring signal is detected. This is a Schmitt trigger input. An RC network may be connected to this pin in order to hold the pin voltage below 2.2V between the peaks of the ringing signal. This pin controls internal power up and activates the partial circuitry needed to determine whether the incoming ring is valid or not. The input is a Schmitt trigger input. The output cell structure is an NMOS output. This input pin is connected to the tip side of the twisted pair wires. It is internally biased to 1/2 VDD when the device is in power up mode. This pin must be DC isolated from the line. This input pin is connected to the ring side of the twisted pair wires. It is internally biased to 1/2 VDD when the device is in power up mode. This pin must be DC isolated from the line. This open drain output goes low when a valid ringing signal is detected. When connected to PDWN pin, this pin can be used for auto power up. This open drain output goes low indicating that a valid carrier is present on the line. A hysteresis is built-in to allow for a momentary drop out of the carrier. When connected to PDWN pin, this pin can be used for auto power up. This pin presents the output of the demodulator when chip in power up mode. This data stream includes the alternate 1 and 0 pattern, the marking, and the data. At all other times, this pin is held high. This output presents the output of the demodulator when chip in power up mode and when an internal validation sequence has been successfully passed. This data stream does not include the alternate 1 and 0 pattern. This pin is always held high. Output pin for testing purposes only. No connection 3/4 3/4 I Power-VDD is the input power for the internal logic. Ground-VSS is ground connection for the internal logic. A logic 1 on this pin puts the chip in power down mode. When a logic 0 is on this pin, the chip in power up mode. This is a Schmitt trigger input. I/O Description
Ring Detections RDET1 RDET2 I I
RTIME
I/O
FSK Signal Inputs TIP RING I I
Detection Results RDET O
CDET
O
DOUT
O
DOUTC TEST NC
O O 3/4
Rev. 1.40
2
September 30, 2002
HT9032C/HT9032D
Absolute Maximum Ratings
Voltages are referenced to VSS, except where noted. Supply Voltage .........................................-0.5V to 6.0V Operating Temperature Range ...................0C to 70C All Input Voltages.................................................25mW Storage Temperature Range ................-40C to 150C
Note: These are stress ratings only. Stresses exceeding the range specified under Absolute Maximum Ratings may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
D.C. Characteristics
Symbol VDD IDD1 IDD2 Parameter Supply Voltage Supply Current Supply Current Test Conditions VDD 3/4 5V 5V Conditions 3/4 PDWN=0 (3.58MHz OSC on) PDWN=1 and RTIME=0 (3.58MHz OSC on and internal circuits partially on) PDWN=1 and RTIME=1 (3.58MHz OSC off) 3/4 3/4 IOL=1.6mA IOH=0.8mA 3/4 RDET1, RTIME, PDWN RDET1, RTIME, PDWN RDET2 TIP, RING
Crystal=3.58MHz, Ta=0~70C Min. 3.5 3/4 3/4 3/4 3/4 0.8V 3/4 0.9V -1 2.0 2.5 1.0 3/4 Typ. 5 3.2 1.9 Max. 5.5 5 2.5 Unit V mA mA
ISTBY VIL VIH IOL IOH IIN VTVT+ VTRDET2 RIN
Standby Current Input Voltage Logic 0 Input Voltage Logic 1 Output Voltage Logic 0 Output Voltage Logic 1 Input Leakage Current, All Inputs Input Low Threshold Voltage Input High Threshold Voltage Input Threshold Voltage Input DC Resistance
5V 5V 5V 5V 5V 5V 5V 5V 5V 5V
3/4 3/4 3/4 3/4 3/4 3/4 2.3 2.75 1.1 500
1 0.2V 3/4 0.1V 3/4 1 2.6 3.0 1.2 3/4
mA VDD VDD VDD VDD mA V V V kW
T IP R IN G RDET1 RDET2 R T IM E PDW N VSS ~
VDD DOUTC DOUT CDET RDET X1 X2
0 .1 m .
H T9032C
3 .5 8 M H z 10M W 30p.
S u p p ly c u r r e n t te s tin g : A ll, e x c e p t P D W N a n d R T IM E , u n w ir e d p in s a r e le ft flo a tin g .
Rev. 1.40
3
September 30, 2002
HT9032C/HT9032D
A.C. Characteristics - FSK Detection
VSS=0V, Crystal=3.58MHz, Ta=0 to 70C, 0dBm=0.7746Vrms @ 600W Symbol Parameter Input Sensitivity: TIP, RING S/N Signal to Noise Ratio Band Pass Filter 60Hz 550Hz 2700Hz 3300Hz Carrier Detect Sensitivity tDOSC tSUPD tDAQ tDCH Oscillator Start Up Time Power Up to FSK Signal Set Up Time Carrier Detect Acquisition Time End of Data to Carrier Detect High Test Conditions VDD 5V 5V Conditions Min. -40 3/4 Typ. Max. Unit -45 20 -64 -4 -3 -34 -48 2 3/4 14 3/4 3/4 3/4 dBm dB
5V
Frequency Response Relative to 1700Hz @ 0dBm
3/4
3/4
dB
5V 5V 5V 5V 5V 3/4 3/4 3/4 3/4
3/4 3/4 15 3/4 8
3/4 3/4 3/4 3/4 3/4
dBm ms ms ms ms
2 Sec 0 .5 S e c R in g S ig n a l tD R T IM E 0 1 0 1 0 1 .. 1 DATA 0 .5 S e c
OSC
RDET tS
PDW N
UPD
CDET
tD
AQ
tD Raw DATA
CH
DOUT
DOUTC
C ooked D A TA
X1
3 .5 8 M H z
Rev. 1.40
4
September 30, 2002
HT9032C/HT9032D
Functional Description
The HT9032 is designed to be the physical layer demodulator for products targeted for the caller ID market. The data signaling interface should conform to Bell 202, which is described as follows:
* Analog, phase coherent, frequency shift keying * Logical 1 (Mark)=1200+/-12Hz * Logical 0 (Space)=2200+/-22Hz * Transmission rate=1200bps * Data application=serial, binary, asynchronous * Logical 0 (Space)=2100Hz * Transmission rate=1200bps
Since the band pass filter of the HT9032 can pass the V.23 signal, hence the HT9032 also can demodulate the V.23 signal. Ring detection The data will be transmitted in the silent period between the first and second power ring before a voice path is established. The HT9032 should first detect a valid ring and then perform the FSK demodulation. The typical ring detection circuit of the HT9032 is depicted below. The power ring signal is first rectified through a bridge circuit and then sent to a resistor network that attenuates the incoming power ring. The values of resistors and capacitor given in the figure have been chosen to provide a sufficient voltage at RDET1 pin to turn on the Schmitt trigger input with approximately a 40 Vrms or greater power ring input from tip and ring. When VT+ of the Schmitt is exceeded, the NMOS on the pin RTIME will be driven to saturation discharging capacitor on RTIME. This will initialize a partial power up, with only the portions of the part involved with the ring signal analysis enabled, including RDET2 pin. With RDET2 pin enabled, a portion of the power ring above 1.2V is fed to the ring analysis circuit. Once the ring signal is qualified, the RDET pin will be sent low.
The interface should be arranged to allow simple data transmission from the terminating central office, to the CPE (Customer Premises Equipment), only when the CPE is in an on-hook state. The data will be transmitted in the silent period between the first and second power ring before a voice path is established. The transmission level from the terminating C.O. will be -13.5dBm+/-1.0. The worst case attenuation through the loop is expected to be -20dB. The receiver therefore, should have a sensitivity of approximately -34.5dBm to handle the worst case installations. The ITU-T V.23 is also using the FSK signaling scheme to transmit data in the general switched telephone network. For mode 2 of the V.23, the modulation rate and characteristic frequencies are listed below:
* Analog, phase coherent, frequency shift keying * Logical 1 (Mark)=1300Hz
PDW N
V
270kW
DD
R T IM E PowerUp L o g ic
0 .2 m .
To B r id g e
470kW 18kW
RDET1
In te rn a l PowerUp L o g ic RDET
RDET2 15kW 1 .2 V
R in g A n a ly s is C ir c u it
Operation mode There are three operation modes of the HT9032. They are power down mode, partial power up mode, and power up mode. The three modes are classified by the following conditions: Modes Power down Partial power up Power up Conditions PDWN=1 and RTIME=1 PDWN=1 and RTIME=0 PDWN=0 <1mA 1.9mA typically 3.2mA typically Current Consumption
Rev. 1.40
5
September 30, 2002
HT9032C/HT9032D
Normally, the PDWN pin and the RTIME pin control the operation mode of the HT9032. When both pins are HIGH, the HT9032 is set at the power down mode, consuming less than 1mA of supply current. When a valid power ring arrives, the RTIME pin will be driven below VT- and the portions of the part involved in the ring signal analysis are enabled. This is partial power up mode, consuming approximately 1.9mA typically. Once the PDWN pin is below VT-, the part will be fully powered up, and ready to receive FSK. During this mode, the device current will increase to approximately 3.2mA (typ). The state of the RTIME pin is now a dont care as far as the part is concerned. After the FSK message has been received, the PDWN pin can be allowed to return to VDD and the part will return to the power down mode.
Application Circuits
Application circuit 1
T IP V
~
DD
0 .2 m .
0 .0 1 m .
~
200kW 9V
H T1050 0 .1 m .
0 .2 m . R IN G
470kW 0 .0 1 m . 200kW T IP R IN G VDD DOUT
18kW
MCU
15kW
PDW N VSS
X1 X2 30p.
3 .5 8 M H z 10M W 30p.
H T9032D
Application circuit 2
T IP V
~
DD
0 .2 m .
0 .0 1 m .
~
200kW 9V
H T1050 0 .1 m .
0 .2 m . R IN G
470kW 20kW 0 .0 1 m . 200kW T IP R IN G RDET1 18kW V 15kW 270kW 0 .2 m .
DD
20kW
VDD DOUTC DOUT CDET RDET X1 X2 30p. MCU
RDET2 R T IM E PDW N VSS
3 .5 8 M H z 10M W 30p.
H T9032C
Rev. 1.40
6
September 30, 2002
HT9032C/HT9032D
Application circuit 3 3/4 power on reset
T IP V
~
DD
0 .2 m .
0 .0 1 m .
~
200kW 9V
H T1050 0 .1 m .
0 .2 m . R IN G
470kW 0 .0 1 m . V C
1
200kW
DD
T IP R IN G
VDD DOUT
18kW
MCU
15kW R
1
PDW N VSS
X1 X2
3 .5 8 M H z 10M W 30p. 30p.
H T9032D
Application circuit 4 3/4 power on reset
T IP V
~
0 .2 m .
DD
0 .0 1 m .
~
200kW 9V
H T1050 0 .1 m .
0 .2 m . R IN G
470kW 20kW 0 .0 1 m . 200kW T IP R IN G RDET1 V C
1
20kW
VDD DOUTC DOUT CDET RDET X1 X2 30p. MCU
18kW
DD
RDET2 V
DD
R T IM E PDW N VSS
15kW
270kW 0 .2 m .
3 .5 8 M H z 10M W 30p.
R
1
H T9032C
VDD
PDW N
V
T
-
X1 3 .5 8 M H z s ta b le
Note: reference C1=0.1mF R1=81kW
Rev. 1.40
7
September 30, 2002
HT9032C/HT9032D
Package Information
8-pin DIP (300mil) outline dimensions
A B 1 8 5 4
H C D E . G
=
I
Symbol A B C D E F G H I a
Dimensions in mil Min. 355 240 125 125 16 50 3/4 295 335 0 Nom. 3/4 3/4 3/4 3/4 3/4 3/4 100 3/4 3/4 3/4 Max. 375 260 135 145 20 70 3/4 315 375 15
Rev. 1.40
8
September 30, 2002
HT9032C/HT9032D
16-pin DIP (300mil) outline dimensions
A 16 B 1 9 8
H C D E . G
=
I
Symbol A B C D E F G H I a
Dimensions in mil Min. 745 240 125 125 16 50 3/4 295 335 0 Nom. 3/4 3/4 3/4 3/4 3/4 3/4 100 3/4 3/4 3/4 Max. 775 260 135 145 20 70 3/4 315 375 15
Rev. 1.40
9
September 30, 2002
HT9032C/HT9032D
8-pin SOP (150mil) outline dimensions
A 1
8
5 B 4
C
C' G D E .
H
=
Symbol A B C C D E F G H a
Dimensions in mil Min. 228 149 14 189 53 3/4 4 22 4 0 Nom. 3/4 3/4 3/4 3/4 3/4 50 3/4 3/4 3/4 3/4 Max. 244 157 20 197 69 3/4 10 28 12 10
Rev. 1.40
10
September 30, 2002
HT9032C/HT9032D
16-pin SOP (300mil) outline dimensions
16 9 A
B 1 8 C C' G H
D E .
=
Symbol A B C C D E F G H a
Dimensions in mil Min. 394 290 14 390 92 3/4 4 32 4 0 Nom. 3/4 3/4 3/4 3/4 3/4 50 3/4 3/4 3/4 3/4 Max. 419 300 20 413 104 3/4 3/4 38 12 10
Rev. 1.40
11
September 30, 2002
HT9032C/HT9032D
Product Tape and Reel Specifications
Reel dimensions
T2 D
A
B
C
T1
SOP 8N Symbol A B C D T1 T2 Description Reel Outer Diameter Reel Inner Diameter Spindle Hole Diameter Key Slit Width Space Between Flange Reel Thickness Dimensions in mm 3301.0 621.5 13.0+0.5 -0.2 2.00.15 12.8+0.3 -0.2 18.20.2
SOP 16W (300mil) Symbol A B C D T1 T2 Description Reel Outer Diameter Reel Inner Diameter Spindle Hole Diameter Key Slit Width Space Between Flange Reel Thickness Dimensions in mm 3301.0 621.5 13.00.5 -0.2 2.00.5 16.8+0.3 -0.2 22.20.2
Rev. 1.40
12
September 30, 2002
HT9032C/HT9032D
Carrier tape dimensions
D
E . W C
P0
P1
t
B0
D1
P
K0 A0
SOP 8N Symbol W P E F D D1 P0 P1 A0 B0 K0 t C Description Carrier Tape Width Cavity Pitch Perforation Position Cavity to Perforation (Width Direction) Perforation Diameter Cavity Hole Diameter Perforation Pitch Cavity to Perforation (Length Direction) Cavity Length Cavity Width Cavity Depth Carrier Tape Thickness Cover Tape Width Dimensions in mm 12.0+0.3 -0.1 8.00.1 1.750.1 5.50.1 1.550.1 1.5+0.25 4.00.1 2.00.1 6.40.1 5.200.1 2.10.1 0.30.05 9.3
SOP 16W (300mil) Symbol W P E F D D1 P0 P1 A0 B0 K0 t C Description Carrier Tape Width Cavity Pitch Perforation Position Cavity to Perforation (Width Direction) Perforation Diameter Cavity Hole Diameter Perforation Pitch Cavity to Perforation (Length Direction) Cavity Length Cavity Width Cavity Depth Carrier Tape Thickness Cover Tape Width Dimensions in mm 16.00.2 12.00.1 1.750.1 7.50.1 1.5+0.1 1.5+0.25 4.00.1 2.00.1 10.90.1 10.80.1 3.00.1 0.30.05 13.3
Rev. 1.40
13
September 30, 2002
HT9032C/HT9032D
Holtek Semiconductor Inc. (Headquarters) No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan Tel: 886-3-563-1999 Fax: 886-3-563-1189 http://www.holtek.com.tw Holtek Semiconductor Inc. (Taipei Sales Office) 4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan Tel: 886-2-2655-7070 Fax: 886-2-2655-7373 Fax: 886-2-2655-7383 (International sales hotline) Holtek Semiconductor Inc. (Shanghai Sales Office) 7th Floor, Building 2, No.889, Yi Shan Rd., Shanghai, China 200233 Tel: 021-6485-5560 Fax: 021-6485-0313 http://www.holtek.com.cn Holtek Semiconductor Inc. (Shenzhen Sales Office) 5/F, Unit A, Productivity Building, Cross of Science M 3rd Road and Gaoxin M 2nd Road, Science Park, Nanshan District, Shenzhen, China 518057 Tel: 0755-8616-9908, 8616-9308 Fax: 0755-8616-9533 Holtek Semiconductor Inc. (Beijing Sales Office) Suite 1721, Jinyu Tower, A129 West Xuan Wu Men Street, Xicheng District, Beijing, China 100031 Tel: 010-6641-0030, 6641-7751, 6641-7752 Fax: 010-6641-0125 Holtek Semiconductor Inc. (Chengdu Sales Office) 709, Building 3, Champagne Plaza, No.97 Dongda Street, Chengdu, Sichuan, China 610016 Tel: 028-6653-6590 Fax: 028-6653-6591 Holmate Semiconductor, Inc. (North America Sales Office) 46729 Fremont Blvd., Fremont, CA 94538 Tel: 510-252-9880 Fax: 510-252-9885 http://www.holmate.com
Copyright O 2002 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holteks products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw.
Rev. 1.40
14
September 30, 2002

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